Portable devices such as digital cameras and music players comprise non-volatile memory units. These portable devices have become smaller in recent years, as have the respective memory units. It is assumed that the miniaturization of portable devices will proceed. In order to fulfill the need for improved performance of the device the amount of data that can be stored in the non-volatile memory unit may increase. As a result, for example more music, photos or other data can be stored in smaller devices.
Non-volatile memory units may be designed in the form of electrical erasable programmable read-only memory (EEPROM). The EEPROM can be electrically programmed and electrically erased. It retains stored data for a long time without a power supply and can easily be programmed and erased many times.
The EEPROM comprises a plurality of memory cells for storing small pieces of information. Memory cells may enable to store only one bit. Multi-bit memory cells, however, can store more than one bit. A so-called nitride programmable read-only memory cell (NROM cell) is operable to store two bits. The NROM cell is described in U.S. Pat. No. 6,011,725.
An embodiment of the NROM memory cell comprises a transistor body that includes a cell well, having a first and a second doping area. A channel region is located between the doping areas. A gate electrode is arranged above the channel region insulated by a dielectric layer, which is arranged between the channel region and the gate electrode. The dielectric layer comprises a first oxide layer, a nitride layer, e.g., silicon nitride, and a second oxide layer. The nitride layer of such a memory cell serves as a charge-trapping layer sandwiched between the insulating oxide layers, which avoid vertical retention. Alternative material for forming the charge-trapping layer, are also possible.
Two individual bits are stored in different regions of the nitride layer. A first bit region is near the first doping area and a second bit region is near the second doping area.
The bits are programmed by means of channel hot electron programming. Electrons are injected from the channel into the charge-trapping layer. Programming of the first bit is performed by applying programming potential to the first doping area and to the gate, while grounding the second doping area. Typically, programming potentials of 9 V are applied to the gate and of 4.5 V are applied to the first doping area, respectively. Thus, the electrons are injected and trapped into the first bit region, which is adjacent to the first doping area. Likewise, programming of a second bit is performed by applying the programming potentials to the second doping area and to the gate while grounding the first doping area. In this case, the electrons are injected and trapped into the second bit region. Typically, the programming potentials are applied repeatedly in such a way that pulses are applied to the memory cells.
For erasing a bit, injection of hot holes generated by band to band tunnelling can be used. Erasing of the first bit is performed by applying erasing potentials to the gate or to the first doping area and the gate. Typically, about 8 V are applied to the first doping area and a negative voltage related to ground is applied to the gate. The applied voltages result in a lateral field. Holes are caused to flow through the bottom oxide layer for compensating the charge of the electrons, which are trapped. The second bit is erased by applying the respective erasing potentials to the gate and to the second doping area.
The bit is read by applying a reverse voltage between the first and second doping area compared to the programming voltage that is used to program this bit. Typically, a reading potential of 1.5 V is applied to the second doping area while grounding the first one, in order to read the first bit. Relatively small charges near the first doping area prevent or reduce current flow. The current flows while there is no trapped charge inside the first bit region. Reading the second bit is performed by applying the respective reading potential to the first doping area while grounding the second one.
A memory cell array includes a plurality of memory cells arranged as a matrix, having rows and columns. One of a plurality of wordlines connects the gate electrodes, which are arranged in the same row. The first doping areas of memory cells which are arranged in the same column and the second doping areas of the memory cells arranged in the adjacent column, form a bitline between these two columns of memory cells. Thus, a potential applied to one of the wordlines is applied to the gate electrode of each memory cell of that row. Likewise, a potential that is applied to one of the bitlines is applied to the first doping area of the memory cells located on one side of that bitline and to the second doping area of the memory cells located on the other side of that bitline.
Each memory cell can be identified by the wordline and the bitlines on either side, which are coupled to that memory cell. Thus, programming, erasing or reading of one of the memory cells is performed by applying the programming potentials, erasing potentials or reading potentials, respectively, to the wordline and the bitlines connected to that memory cell.
The bitlines are coupled to a bitline decoder. The wordlines are coupled to a wordline decoder. The bitline decoder is operable to apply the programming, reading or erasing potentials to each bitline, in particular to a pair of adjacent bitlines in order to program, read or erase the memory cells coupled to these two bitlines. The wordline decoder is operable to apply the programming or erasing potential to each of the wordlines. The bitline decoder and the wordline decoder are coupled to an address decoder, which is operable to identify the memory cells to be programmed, erased or read. The address decoder is further operable to control the bitline decoder and the wordline decoder, in order to access these memory cells.
Programming may be performed in a row or in a column. That means, the programming of several memory cells, which are located in the same column, may be performed by applying the programming potentials to the two bitlines, which are connected to the memory cells of the column and to the wordlines, which are connected to the memory cells to be programmed. Thus, either the first bits or the second bits are programmed. Programming the other bits of the memory cells in this word is performed by switching the programming potentials applied to the bitlines. Thus, two separate programming steps, including charging and decharging the bitlines, are necessary in order to program the first and second bits.
Likewise, the memory cells located in the same row can be programmed by applying the programming potentials to one wordline and a plurality of bitlines.
Charging the bitlines is time and power consuming. The bitlines require a large amount of energy to be loaded into it and to be charged to the right programming voltage level. The loading of the bitlines occur each time a programming pulse has to be applied. The required energy and a current consumption due to charging, depend on the length of the bitlines and the number of bitlines, which are loaded in parallel. The current consumption may be a limiting factor in the architecture of long bitlines and also limits the number of columns or rows to be programmed in parallel.